AI - UVM Verification Engineer

Role Description: This is a full-time remote role for a UVM Verification Engineer. Using leading AI tools, the UVM Verification Engineer will develop and maintain System Verilog/UVM testbenches, including stimulus generation, checkers, monitors, and scoreboards to verify complex RTL designs. Responsibilities include creating test plans, writing and executing tests, debugging simulation failures, and collaborating closely with design, validation, and architecture teams to ensure functional correctness and coverage goals. The engineer will analyze verification results, track defects, refine test environments, and contribute to continuous improvement of verification methodologies and automation. The role may also involve mentoring other team members, reviewing verification collateral, and supporting client-facing technical discussions when needed.

Qualifications: AI experience or interest in learning AI for verification. Strong RTL Design and Functional Verification skills, including experience with System Verilog and UVM.Proficiency in Debugging and Validation of complex digital designs using simulation and related tools. Understanding of Good Manufacturing Practice (GMP) or similar quality and process compliance frameworks, where applicable. Experience with EDA tools (simulators, waveform viewers, coverage tools) and version control systems. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Ability to work effectively in a remote, distributed team, with clear written and verbal communication skills. Familiarity with scripting languages (e.g., Python, Perl, or shell) to automate verification workflows is beneficial. Background in ASIC/SoC design flows and knowledge of standard bus protocols (e.g., AXI, PCIe) is a plus.