Senior Silicon Engineer

What You'll Do: Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon. Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code. Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness. Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic. Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods. Grow and mentor the silicon team as the company scales.

What We're Looking For: 8 or more years of hands‑on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs. Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs. End‑to‑end FPGA experience: RTL through synthesis, place‑and‑route, and deployment to working hardware. Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture. Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows. Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools. Background designing or optimizing AI accelerators or low‑level AI kernel implementations. Tapeout experience, high‑speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages. Self-directed, comfortable with ownership, and energized by fast‑moving environments.

Compensation & Benefits: Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available. Location Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.