AI-Driven UVM Verification Engineer

Posted yesterday

eda technology futuresMillbrae (CA)

SENIORITY

Lead

Apply

About the role

An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite team, you will develop and deploy UVM testbenches, collaborating closely with machine learning and software engineers. This position is perfect for those eager to explore AI-integrated semiconductor design and make a significant impact in the industry. Join a mission-driven team that is reshaping the future of chip verification and development.

Before you apply

Applying takes about a minute. These four things decide how fast it moves after that.

Your profile is current

It's what we read first. Occupations, seniority and locations matter more than a long history.

Two examples you can talk through

Not a portfolio — just two pieces of work where you can explain the decisions and what you'd change.

A number in mind

What you're on now and what would make you move. We negotiate better when we know both.

Your notice period

Employers plan around it, and it's the question that stalls offers most often.

Once you apply, someone reads it and calls you before anything reaches the employer — usually within two working days.

More like this